1. Field of the Invention
The present invention relates to a logic simulation on system which simulation the logic operation of the semiconductor integrated circuit using a computer system and particularly relates to a logic simulation system for the logic simulation considering variation inside the chip within the semiconductor integrated circuit.
2. Description of the Related Art
The computerized logic simulation system for simulation of the logic operation applicable to semiconductor integrated circuit has been developed. In such a logic simulation system, in general, the logic cells used for execution of the logic simulation have, in a library, delay values within the variation range of the fabrication conditions for the semiconductor integrated circuit as the subject of the simulation. For each logic cell inside the semiconductor integrated circuit, the delay value is determined by adding the wiring delay to the delay value in such library. Therefore, the logic cells having the same function name and the same wiring length have the same delay value in the logic simulation.
In a chip in reality (actual chip), however, there are slight variations in wire diameter and thickness and gate oxide film thickness because of fabrication factors, which results in variation in delay values. Such variation is called the chip inside variation. When there are some chip inside variations in the route of the signal input to the combination circuit, they just change the delay time in the combination circuit and cause any affect logically. However, when the chip inside variation exists in the route of the signal input to a logic cell in the flip-flop (F/F) system, it may change not only the delay time but also the output logic from the logic cell in the F/F system For example, when the F/E' has a large chip inside variation, the signal route on the clock side and a small variation in the signal route on the data side, the F/F setup specification or the hold specification is not satisfied.
To execute the logic simulation considering the chip inside variation, different delay values need to be provided to the logic cells having the same function. However whether the delay should be increased or decreased for chip inside variation depends on the signal route, and such delay values cannot be determined until the connection relations between the logic cells are fixed. Further, when the signal route is branched, the variation tendency cannot be determined for the logic cells existing on the signal route before such branch. Therefore, such simulation cannot be executed by the ordinary logic simulation method using the above conventional logic simulation system.
A method to provide different delay values to the logic cells having the same function in the logic simulation has been conventionally proposed. A conventional logic simulation method of this type is the technology disclosed in Japanese Patent Application Laid-open (Kukai) No. Heisei 63-98042 "Simulation Method".
FIG. 21 is a flowchart illustrating in general the logic simulation processing described in the above laid-open invention. Referring to the figure, the connection data and the logic verification pattern are read at Step 2101. At Step 2102, a table to store delay values is prepared. In this case, the table has a width corresponding to the total number of logic cells "N" contained in the connection data and a depth corresponding to the pattern length "M" of the logic verification pattern. Then, at Step 2103, delay values for the logic cells contained in the connection data are determined by the formula (1) below according to the standard value (TYP), the maximum value (MAX) and the minimum value (MIN) of the logic cell delay in the delay library. EQU Delay value=MIN+(MAX-MIN).times.(random number) (1)
Calculation using formula (1) is executed for the number of logic verification patterns for all logic cells contained in the connection data. The calculation results are stored as the delay values on the table. The random number in the above formula (1) is the distribution function most approximated to the actual logic cell variation. For example, the random number based on the normal distribution may be supposed. The above procedure from Step 2101 to step 2103 is executed as the pre-processing of the logic simulation.
At Step 2104, the delay value for the logic cells stored at the first item pattern on the table are read. At Step 2105, using the connection data, the logic verification pattern and the table, the delay value on the table corresponding to the first pattern in the logic verification patterns is read out so that the operation analysis with certain logic simulation processing is executed. The delay values for the logic cells on the table are set approximately to the actual variations in the range from the minimum value (MIN) to the maximum value (MAX). Thus, the chip inside variation for all logic cells can be verified.
At Step 2106, the result of the operation analysis executed at step 2105 is output. At Step 2107, it is judged whether the pattern subjected to processing from Step 2104 to Step 2106 is the final item pattern of the table or not. If it is not the final pattern, the system returns to the processing at step 2104, reads the delay value stored at the next item pattern on the table and proceeds to the operation analysis (Step 2105) and the analysis result output (Step 2106).
If, at Step 2107, the pattern subjected to the processing from Step 2104 to Step 2106 is the pattern of the final item on the table, the processing is terminated.
As described above, a conventional logic simulation system in general extracts some values suitable for certain fabrication condition in advance from the delay value library as the delay values for the logic cell to be referred to and, with the delay value for each logic cell inside a chip fixed, calculates the response to the applied pattern. This enables high speed operation processing. However, since the delay value for each logic cell is fixed inside the chip, it cannot always execute the logic simulation correctly.
On the other hand, the above conventional logic simulation system citing the delay value for each logic cell from the table for each pattern can correctly reflect the delay value for each logic cell, but it takes time for processing since it requires a step to refer to the table to cite a delay value.
In addition, the above table has a size defined by (Total number of logic cells N).times.(Pattern length M). When the scale of the semiconductor integrated circuit becomes large and the pattern length becomes longer, it takes time to prepare the table and requires an excessively large memory size for table preparation, which results in cost increase.
Further, since the delay values are set without paying attention to the signal route of the flip-flop, variation in the delay values are averaged when there are many logic steps in the signal route. In such case, whether there is any problem about operation timing cannot be verified.
Besides, the simulation results obtained by the above conventional logic simulation system only tells whether or not there is any problem about variation effect. Even when there is a problem about internal timing, it cannot specify the F/F causing such problem.